Design synthesizable USB 3.0 using Verilog HDL and simulate design using Cadence

In this project I design USB 3.0 using Verilog HDL and simulate the design in Cadence. My design mainly includes two layers of USB 3.0, Physical Layer and Link Layer. Along with USB 2.0 functionality it includes Superspeed functionality .Physical Layer contains PCI Express and PIPE interface. The design transferred data from transmitter to receiver serially. In the project I manage to transfer data either on 2.5GT/s or on 5.0GT/s depends upon the mode and rate. The design generates clock that runs on two different frequencies i.e. 125MHz and 250MHz that used to transfer data on parallel interface. In Design I manage to capture the data that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data. The Link Layer contains Link Transition and Status State Machine (LTSSM). This is used to manage the link between two ports. It manages the Superspeed and Power of the link by putting the link into appropriate stage according to its usage.