In-Field processor failure prediction using gate level characterization

Predicting failure of integrated circuits is typically a destructive process that modifies the circuit in order to monitor and collect data. A non-destructive method of failure prediction is analyzed by simulating circuit activity in custom software, applying a technique known as gate level characterization (GLC) to calculate properties of a circuit's logic gates. To monitor circuit use and aging, measurements from the circuit are taken before and after an aging model is applied to the circuit. This method can be a viable alternative to destructive monitoring techniques, as it can be implemented in software without the need for alteration of existing hardware.