Digital datapath for an image acquisition system

The Digital Datapath for an Image Acquisition System (IAS) describes the architecture of an FPGA-based system designed to capture, process, and transmit image data generated by an array of photo-detectors. Due to the substantial number of photo-detectors in the array, two of the most significant challenges and focuses of this project are to capture incoming image data simultaneously, and to organize it into a format which lends itself for serial transmission to the final destination. To accomplish these tasks, a memory mapping and data processing algorithm is implemented over two FPGA stages. The necessity for the IAS originates from the lack of hardware support between a long-range image targeting system, and a data processing application which reconstructs an image from the indistinguishable captured data. The objective of this graduate project is to design a system which meets the set of specified requirements, and to simulate the logic which controls the IAS datapath.