Application Specific Integrated Circuit for infiniband architecture

This project is based on implementing Application Specific Integrated Circuit (ASIC) for Infniband Architecture. This ASIC is for the Link Layer of the OSI (Open Systems Interconnection) network model. The link layer handles the sending and receiving of data across the links at the packet level. It mainly deals with addressing, buffering, flow control, error detection and switching. Infiniband is one of the data communication and networking protocol which deals with interconnecting processor nodes and I/O nodes to form a system area network. The architecture is independent of the host operating system (OS) and processor platform. Current interconnect technologies have failed to keep pace with computer evolution. We have microprocessors delivering data at blistering speeds but I/O subsystem still is not capable of receiving and processing data at such speed. InfiniBand architecture tries to eliminate this bottleneck. I have implemented the Link engine of this architecture on a chip using Cadence and Synopsys tools. The design is implemented on Synopsys 90nm technology and also on Artisan 180nm technology. I have done a comparative study using EDA tools and libraries on area, speed and power. The purpose of this project is to get mainly exposed to Back end design flow of ASIC. I had a verified IP of Infiniband Link Engine. To implement the design on ASIC, I had to link the design to specific library using EDA tools of Synopsys and Cadence. I used Design Compiler from Synopsys to get the netlist of the design which is later then given as an input to IC compiler tool to perform floorplanning, placement and routing to get the final GDSII. I have also used Cadence's RTL compiler to get the netlist for the design. The main objective of this project is to get the ASIC flow using Synopsys and Cadence tools. In order to get the flow, I took Link Engine of Infiniband Architecture as a design.