Backend design and testability of a digital ASIC

Very Large Scale Integration (VLSI) Design is an important and complex area of Electrical and Computer Engineering field. It uses many Computer Aided Design (CAD) tools. There are three parts of CAD tools: Design management, Verification, and Synthesis. Application Specific Integrated Circuit (ASIC) design uses many of the Electronic Design Automation (EDA) tools for Designing, testing, and verification. Advanced Electronic Design Automation (EDA) tools like TetraMAX, Design Compiler, PrimeTime, and IC Compiler from Synopsys are necessary tools in today’s complex IC-chip design. The main aim of this project is to design and test a digital ASIC using these advanced design tools. The project also provides a brief knowledge of ASIC design flow (Front-end and Back-end), Design Compiler, Synopsys DFT compiler, Synopsys TetraMAX, and Synopsys PrimeTime. A design example has been implemented to demonstrate a complete top-down design flow for this process. By using these tools, designers can optimize power, area, and timing for the final chip fabrication.