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dc.contributor.advisor Roosta, Ramin en_US
dc.contributor.author Pandya, Parth
dc.date.accessioned 2018-02-13T17:43:16Z
dc.date.available 2018-02-13T17:43:16Z
dc.date.copyright 2018 en_US
dc.date.issued 2018-02-13
dc.identifier.uri http://hdl.handle.net/10211.3/199956
dc.description Includes bibliographical references (pages 52-52) en_US
dc.description.abstract Very Large Scale Integration (VLSI) Design is an important and complex area of Electrical and Computer Engineering field. It uses many Computer Aided Design (CAD) tools. There are three parts of CAD tools: Design management, Verification, and Synthesis. Application Specific Integrated Circuit (ASIC) design uses many of the Electronic Design Automation (EDA) tools for Designing, testing, and verification. Advanced Electronic Design Automation (EDA) tools like TetraMAX, Design Compiler, PrimeTime, and IC Compiler from Synopsys are necessary tools in today’s complex IC-chip design. The main aim of this project is to design and test a digital ASIC using these advanced design tools. The project also provides a brief knowledge of ASIC design flow (Front-end and Back-end), Design Compiler, Synopsys DFT compiler, Synopsys TetraMAX, and Synopsys PrimeTime. A design example has been implemented to demonstrate a complete top-down design flow for this process. By using these tools, designers can optimize power, area, and timing for the final chip fabrication.
dc.description.statementofresponsibility by Parth Pandya en_US
dc.format.extent ix, 61 pages en_US
dc.language.iso en_US en_US
dc.publisher California State University, Northridge en_US
dc.rights.uri http://scholarworks.csun.edu/xmlui/handle/10211.2/286 en_US
dc.subject Application Specific Integrated Circuit (ASIC) design flow
dc.subject Electronic Design Automation(EDA) tools
dc.subject Automatic Test Pattern Generation(ATPG)
dc.subject Design for Testability
dc.subject Low power ASIC
dc.subject Static Timing Analysis
dc.subject Backend design
dc.subject PrimeTime
dc.subject TetraMAX
dc.subject Design compiler
dc.subject.other Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering. en_US
dc.title Backend design and testability of a digital ASIC
dc.type Thesis en_US
dc.date.updated 2018-02-13T17:43:16Z
dc.contributor.department California State University, Northridge. Department of Elec & Comp Engr en_US
dc.description.degree M.S. en_US
dc.contributor.committeeMember Mirzaei, Shahnam en_US
dc.contributor.committeeMember Tabibzadeh, Maryam en_US
dc.rights.license By signing and submitting this license, you the author grant permission to CSUN Graduate Studies to submit your thesis or dissertation, and any additional associated files you provide, to CSUN ScholarWorks, the institutional repository of the California State University, Northridge, on your behalf. You grant to CSUN ScholarWorks the non-exclusive right to reproduce and/or distribute your submission worldwide in electronic or any medium for non-commercial, academic purposes. You agree that CSUN ScholarWorks may, without changing the content, translate the submission to any medium or format, as well as keep more than one copy, for the purposes of security, backup and preservation. You represent that the submission is your original work, and that you have the right to grant the rights contained in this license. You also represent that your submission does not, to the best of your knowledge, infringe upon anyone's copyright. If the submission contains material for which you do not hold copyright, or for which the intended use is not permitted, or which does not reasonably fall under the guidelines of fair use, you represent that you have obtained the unrestricted permission of the copyright owner to grant CSUN ScholarWorks the rights required by this license, and that such third-party owned material is clearly identified and acknowledged within the text or content of the submission. If the submission is based upon work that has been sponsored or supported by an agency or organization other than the California State University, Northridge, you represent that you have fulfilled any right of review or other obligations required by such contract or agreement. CSUN ScholarWorks will clearly identify your name(s) as the author(s) or owner(s) of the submission, and will not make any alterations, other than those allowed by this license, to your submission. en_US


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