Resource sharing and optimization of DFT algorithm for concurrent transforms on reconfigurable hardware

This thesis report presents a novel approach for sharing resources between multiple concurrent DFT instances which can save substantial RC area and optimize latency compared to direct implementation of transforms. We will apply divide and conquer technique and optimized scheduling to minimize resources namely memory, arithmetic and logic used for all transforms. Memory resources proposed in this paper are DFT coefficients and buffers used for intermediate and final results. Highest order transform coefficients are stored in memory and other transforms access same memory portion to fetch desired coefficients. Sharing coefficient technique will not affect performance for lower order transforms. Arithmetic and Logic is partitioned properly into shared and non-shared units which improves resource utilization significantly. An improved latency is achieved compared to direct implementation by applying proper scheduling of data orders which at the same time results in saving FPGA area. This technique presented in this paper is compared to direct implementation of DFT algorithm. For comparison 10 DFTs of length 1024 ,512 ,256 ,128 ,64, 32 ,16 ,8 ,4,2 points was instantiated. Parameters considered are LUTs, FFs, DSP48s and BRAMs. Resource utilization report shows 957 LUTs compared to 1304 (73 %) ,714 FFs compared to 1230 (58 %),3 DSPs compared to 42 (7%),18.5 Bram36k compared to 1374(1.3%). Implementation results shows proposed method can save significant area.